SRAM Chip Async Single 5V 288K-Bit 32K x 9-Bit 15ns 32-Pin SOJ T/R

The CY7C188 is a high-performance CMOS static RAM organized as 32,768 words by 9 bits. Easy memory expansion is provided by an active-LOW chip enable (CE1), an active-HIGH chip enable (CE2), an active-LOW output enable (OE), and tri-state drivers. The device has an automatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking CE1 and write enable (WE) inputs LOW and CE2 input HIGH. Data on the nine I/O pins (I/Oo – I/O8) is then written into the location specified on the address pins (A0 – A14). Reading from the device is accomplished by taking CE1 and OE LOW while forcing WE and CE2 HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The nine input/output pins (I/O0 – I/O8) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C188 is available in standard 300-mil-wide SOJ.

• High speed
  • 15 ns
• Automatic power-down when deselected
• Low active power
  • 660 mW
• Low standby power
  • 55 mW
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE features
• Available in non Pb-free 32-Lead (300-Mil) Molded SOJ