SRAM Chip Async Single 5V 256K-Bit 32K x 8 55ns 28-Pin TSOP-I T/R

The CY62256N is a high performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable and active LOW output enable and tristate drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9 percent when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, and ?? active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.The input/output pins remain in a high impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.

• Temperature ranges
  • Commercial: 0 °C to +70 °C
  • Industrial: -40 °C to +85 °C
  • Automotive-A: -40 °C to +85 °C
  • Automotive-E: -40 °C to +125 °C
• High speed: 55 ns
• Voltage range: 4.5 V to 5.5 V operation
• Low active power
  • 275 mW (max)
• Low standby power (LL version)
  • 82.5 µW (max)
• Easy memory expansion with CE/ and OE/ Features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed and power
• Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP, 28-pin (300-mil) narrow SOIC, 28-pin TSOP I, and 28-pin reverse TSOP I packages