SRAM Chip Async Single 5V 16K-Bit 4K x 4-Bit 20ns 20-Pin PDIP

The CY7C168A is a high-performance CMOS static RAM organized as 4096 by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. The CY7C168A has an automatic power-down feature, reducing the power consumption by 77% when deselected. Writing to the device is accomplished when the Chip Select (CE) and Write Enable (WE) inputs are both LOW. Data on the four data input/output pins (I/O0 through I/O3) is written into the memory location specified on the address pins (A0 through A11). Reading the device is accomplished by taking the Chip Enable (CE) LOW, while Write Enable (WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the four data input/output pins (I/O0 through I/O3). The input/output pins remain in a high-impedance state when Chip Enable (CE) is HIGH or Write Enable (WE) is LOW. A die coat is used to insure alpha immunity.

• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
  • tAA = 15 ns
• Low active power
  • 633 mW
• Low standby power
  • 110 mW
• TTL-compatible inputs and outputs
• VIH of 2.2V
• Capable of withstanding greater than 2001V electrostatic discharge