SRAM Chip Async Single 3V 2M-Bit 128K x 16 70ns 44-Pin TSOP-II

The CY62136V is a high-performance CMOS static RAM organized as 131,072 words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected. The input/output pins are placed in a high-impedance state when: deselected , outputs are disabled, BHE and BLE are disabled , or during a write operation. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable is LOW, then data from I/O pins is written into the location specified on the address pins. Reading from the device is accomplished by taking Chip Enable and Output Enable LOW while forcing the Write Enable HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes.

• Low voltage range:
  • CY62136V: 2.7V-3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE/ and OE/ and features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power