SRAM Chip Async Single 3.3V 8M-Bit 1M x 8 12ns 44-Pin TSOP-II

The CY7C1059DV33 is a high performance CMOS Static RAM organized as 1M words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE/ and OE/), an active LOW Output Enable (), and tri-state drivers. To write to the device, take Chip Enable (CE/ and OE/) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enable (CE/ and OE/) and Output Enable () LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input or output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE/ and OE/HIGH), the outputs are disabled (OE HIGH), or a write operation is in progress (CE/ and OE/LOW and WE LOW). The CY7C1059DV33 is available in 44-pin TSOP-II package with center power and ground (revolutionary) pinout.

• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 110 mA at f = 100 MHz
• Low CMOS standby power
  • ISB2 = 20 mA
• 2.0 V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE/ and OE/ and features
• Available in Pb-free 44-pin TSOP-II package
• Offered in standard and high reliability (Q) grades