SRAM Chip Async Single 3.3V 64M-Bit 8M x 8 12ns 48-Pin FBGA

The CY7C1089DV33 is a high-performance CMOS static RAM organized as 8,388,608 words by 8 bits. To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A22). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) LOW and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 LOW or CE2 HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW).

• High speed
  • tAA: 12 ns
• Low active power
  • ICC: 300 mA at 12 ns
• Low complementary metal oxide semiconductor (CMOS) standby power
  • ISB2: 100 mA
• Operating voltages of 3.3 ± 0.3 V
• 2.0-V data retention
• Automatic power-down when deselected
• Transistor-transistor logic (TTL)-compatible inputs and outputs
• Easy memory expansion with CE1 and CE2 features
• Available in Pb-free 48-ball fine ball grid array (FBGA) package