SRAM Chip Async Single 3.3V 2M-Bit 128K x 16 10ns 44-Pin TSOP-II T/R

The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128 K words by 16 bits. Writing to the device is accomplished by taking Chip Enable and Write Enable inputs LOW. If Byte Low Enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If Byte High Enable (BHE) is LOW, then data from I/O pins is written into the location specified on the address pins.

• Pin and function compatible with CY7C1010CV33
• High speed
  • tAA = 10 ns
• Low active power
  • ICC = 90 mA at 10 ns
• Low CMOS standby power
  • ISB2 = 10 mA
• 2.0 V data retention
• Automatic power down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE/ and OE/ and features
• Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages