SRAM Chip Async Single 3.3V 1M-Bit 64K x 16 12ns 48-Pin FBGA Tray

The CY7C10212CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE\) and Write Enable (WE\) inputs LOW. If Byte Low Enable (BLE\) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE\) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE\) and Output Enable (OE\) LOW while forcing the Write Enable (WE\) HIGH. If Byte Low Enable (BLE\) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE\) is LOW, then data from memory appears on I/O8 to I/O15. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE\ HIGH), the outputs are disabled (OE\ HIGH), the BHE\ and BLE\ are disabled (BHE\, BLE\ HIGH), or during a write operation (CE\ LOW and WE\ LOW).

• Temperature ranges: Automotive-E -40 °C to 125 °C
• Pin and function compatible with CY7C10212CV33
• High speed: tAA = 12 ns (Automotive-E)
• CMOS for optimum speed and power
• Low active power: 325 mW (max)
• Automatic power down when deselected
• Independent control of upper and lower bits
• Available in Pb-free 48-ball FBGA package