SRAM Chip Async Single 2.5V/3.3V 1M-Bit 64K x 16 45ns 44-Pin TSOP-II

The CY62127DV30 is a high-performance CMOS static RAM organized as 64 K words by 16-bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected. The input/output pins are placed in a high-impedance state when: deselected, outputs are disabled, both byte high enable and byte low enable are disabled or during a write operation. Writing to the device is accomplished by taking chip enable and write enable inputs LOW. If byte low enable is LOW, then data from I/O pins, is written into the location specified on the address pins. If byte high enable is LOW, then data from I/O pins is written into the location specified on the address pins. Reading from the device is accomplished by taking chip enable and output enable LOW while forcing the write enable HIGH. If byte low enable is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If byte high enable is LOW, then data from memory appear on I/O8 to I/O15.

• Temperature ranges
  • Industrial:-40 °C to 85 °C
• Very high speed: 55 ns
• Wide voltage range: 2.2 V to 3.6 V
• Pin compatible with CY62127BV
• Ultra-low active power
  • Typical active current: 0.85 mA at f = 1 MHz
  • Typical active current: 5 mA at f = fMAX
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Available in Pb-free 48-ball FBGA and 44-pin TSOP Type II packages