SRAM Chip Async Dual 5V 8K-Bit 1K x 8 25ns 52-Pin PLCC

The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141 are high speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/130A/ CY7C131/131A can be used as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

• True dual-ported memory cells, which allow simultaneous reads of the same memory location
• 1K x 8 organization
• 0.65 micron CMOS for optimum speed and power
• High speed access: 15 ns
• Low operating power: ICC = 110 mA (maximum)
• Fully asynchronous operation
• Automatic power down
• Master CY7C130/130A/CY7C131/131A easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on CY7C140/CY7C141
• INT flag for port-to-port communication
• Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC, 52-pin TQFP
• Pb-free packages available