SRAM Chip Async Dual 3.3V 1.125M-Bit 32K x 36 15ns 144-Pin TQFP Tray

The CY7C057V is a low-power CMOS 16K and 32K x 36 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 36-bit dual-port static RAMs or multiple devices can be combined in order to function as a 72-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 72-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.

• True dual-ported memory cells that allow simultaneous access of the same memory location
• 32 K × 36 organization (CY7C057V)
• 0.25-micron Complimentary metal oxide semiconductor (CMOS) for optimum speed/power
• High-speed access: 12/15 ns
• Low operating power
  • Active: ICC = 250 mA (typical)
  • Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 72 bits or more using Master/Slave Chip Select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Byte select on left port
• Bus matching on right port
• Depth expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 144-pin Thin quad plastic flatpack (TQFP) or 172-ball ball grid array (BGA)
• Pb-free packages available
• Compact packages:
  • 144-pin TQFP (20 × 20 × 1.4 mm)
  • 172-ball BGA (1.0-mm pitch) (15 × 15 × 0.51 mm)