KCU1250 Xilinx Kintex UltraScale FPGA Characterization Kit

The KCU1250 Characterization Kit provides everything you need to evaluate the 20 GTH 16.3Gbps transceivers available on the UltraScale™ XCKU040-FFVA1156 FPGA. Access to both the Integrated Bit Error Ratio Test (IBERT) demonstration and the Vivado® Design Suite enables quick evaluation of the industry leading GTH transceivers. Each GTH Quad and its associated reference clock are routed from the FPGA to the BullsEye connector pad. This enables users to connect to a broad range of evaluation platforms, from backplanes and optical evaluation boards to high speed test equipment.What"s IncludedKintex UltraScale Characterization Board featuring the XCKU040-2FFVA1156E FPGAMGT Power Modules that meets all the power requirements UltraScale FPGA GTH transceiverSuperClock-2 programmable clock moduleSamtec BullsEye Cable for connecting the end users system to the FPGA’s GTH transceivers and reference clocksSMA CablesPower SupplyAccess to Reference Designs & Documentation including board schematic, layout files and moreAccess to Vivado Design Suite: Design Edition - with license for XCKU040 device

• UltraScale XCKU040-2FFVA1156E FPGA
• BullsEye cable access to all 20 GTH transceivers on the UltraScale XCKU040-2FFVA1156E FPGA
• Onboard power supplies for all necessary voltages
• Power connectors for optional use of external power supplies
• Digilent USB JTAG programming port
• System controller (Zynq-7000 AP SoC XC7Z010-CLG225)
• MGT power module supporting UltraScale FPGA GTH transceiver power requirements
• A fixed, 300 MHz 2.5V LVDS oscillator wired to multi-region clock capable (MRCC) inputs
• Two pairs of differential MRCC inputs with SMA connectors
• SuperClock-2 module supporting programmable clock outputs
• Samtec BullsEye connector pads for the FPGA GTH transceivers and reference clocks
• General purpose DIP switches, LEDs, pushbuttons, and test I/O
• Three VITA 57.1 FPGA mezzanine card (FMC) high pin count (HPC) connectors
• USB to dual-UART bridge
• I2C bus
• PMBus connectivity to the boards digital power supplies
• Active cooling for the FPGA