Clock Fanout Buffer 10-OUT 24-Pin SSOP Tube

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable OE input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC. The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications

Operates at 3.3-V V_CC

LVTTL-Compatible Inputs and Outputs

Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)

Distributes One Clock Input to Ten Outputs

Distributed V_CC and Ground Pins Reduce Switching Noise

High-Drive Outputs (-32-mA I_OH, 32-mA I_OL)

State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation

Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages