SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 3ns 165-Pin FBGA Tray
The CY7C1380DV33 SRAM integrates 524,288 × 36 and 1,048,576 × 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive edge triggered clock input (CLK).
- Supports bus operation up to 200 MHz
- Available speed grades is 200 MHz
- Registered inputs and outputs for pipelined operation
- 3.3 V core power supply
- 2.5 V or 3.3 V I/O power supply
- Fast clock-to-output times
- Provides high performance 3-1-1-1 access rate
- User selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences
- Separate processor and controller address strobes
- Synchronous self-timed write
规格参数
| Brand | Rochester Electronics |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 512 kWords |
| Density | 18 Mb |
| Operating temperature | -40 to 85 °C |
| Pin Count | 165 |
| Number Of Ports | 4 |
| Mounting | Surface Mount |
| Address B | 19 Bit |
| Number Of | 36 Bit |
| Number Of | 36 Bit |
| Maximum O | 300 mA |
| Product description | 15 x 13 x 0.89 mm |
| Maximum R | 3 ns |
| Supplier | FBGA |
| Typical O | 3.3000 V |
| ECCN | 3A991.B.2.A |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Country of origin | United States |
| Screening Level | Industrial |
| Minimum O | 3.135 V |
| Maximum O | 3.6 V |
| Maximum C | 200 MHz |
| Data Rate | SDR |
| Architecture | Pipelined |
| Msl Level | 3 |
SKU: CY7C1380DV33-200BZI