SRAM Chip Sync Quad 2.5V/3.3V 18M-Bit 512K x 36 6.5ns/3ns 165-Pin FBGA Tray

The GS8161ExxB(T/D)-xxxV is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP and 165 BGA packages
• RoHS-compliant 100-lead TQFP and 165 BGA packages available
• 14 mm x 22 mm, 119 BGA, Green 13 mm x 15 mm, 165 FPBGA