SRAM Chip Sync Quad 2.5V 36M-Bit 1M x 36 3.4ns 165-Pin FBGA T/R

The CY7C1460AV25 ia a 2.5 V, 1 M × 36/2 M × 18 synchronous pipelined burst SRAMs with No Bus Latency (NoBL logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460AV25 is a equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent write/read transitions. The CY7C1460AV25 is a pin-compatible and functionally equivalent to ZBT devices.

• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
  • Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous
• Fully registered (inputs and outputs) for pipelined operation
• Byte Write capability
• 2.5 V core power supply
• 2.5 V/1.8 V I/O power supply
• Fast clock-to-output times
  • 2.6 ns (for 250-MHz device)
• Clock enable (CE/ and OE/?) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV25 available in JEDEC-standard Pb-free 100-pin TQFP package, Pb-free and non Pb-free 165-ball FBGA package.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst capability - linear or interleaved burst order
• “ZZ” sleep mode option and stop clock option