SRAM Chip Sync Quad 1.8V/2.5V 36M-Bit 1M x 36 7.5ns/3.8ns 165-Pin FBGA Tray

The GS832136E is a 37,748,736-bit high performance synchronous SRA M with a 2- bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
• 32MB or 36MB product family
• 15 mm x 17 mm, 165 FPBGA
• Default to SCD x36 Interleaved Pipeline mode