SRAM Chip Async Single 5V 4M-Bit 1M x 4-Bit 15ns 32-Pin SOJ

The CY7C1046B is a high-performance CMOS static RAM organized as 1,048,576 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE\), an active LOW Output Enable (OE\), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE\) and Write Enable (WE\) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable (CE\) and Output Enable (OE\) LOW while forcing Write Enable (WE\) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the device is deselected (CE\ HIGH), the outputs are disabled (OE\ HIGH), or during a write operation (CE\ LOW, and WE\ LOW). The CY7C1046B is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout.

• High speed: tAA = 12 ns
• Low active power: 935 mW (max.)
• Low CMOS standby power (L version): 2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE\ and OE\ features