SRAM Chip Async Single 5V 1M-Bit 256K x 4-Bit 15ns 28-Pin SOJ

The CY7C1006B is high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable, an active LOW Output Enable, and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. Writing to the devices is accomplished by taking Chip Enable and Write Enable inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins. Reading from the devices is accomplished by taking Chip Enable and Output Enable LOW while forcing Write Enable HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins are placed in a high-impedance state when the devices are deselected, the outputs are disabled, or during a write operation (CE and WE LOW). The CY7C106B is available in a standard 400-mil-wide SOJ; the CY7C1006B is available in a standard 300-mil-wide SOJ.

• High speed
  • tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
  • 495 mW
• Low standby power
  • 275 mW
• 2.0V data retention (optional)
  • 100 µW
• Automatic power-down when deselected
• TTL-compatible inputs and outputs