SRAM Chip Async Single 3V 16M-Bit 2M/1M x 8/16-Bit 45ns 48-Pin VFBGA Tray

The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits or 2M words by 8 bits. This device features an advanced circuit design that provides an ultra low active current. Ultra low active current is ideal for providing More Battery LifeTM (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption by 99 percent when addresses are not toggling. Place the device into standby mode when deselected. The input and output pins are placed in a high impedance state when: the device is deselected, outputs are disabled, both Byte High Enable and Byte Low Enable are disabled, or a write operation is in progress. To write to the device, take Chip Enables and Write Enable input LOW. If Byte Low Enable is LOW, then data from I/O pins is written into the location specified on the address pins. If Byte High Enable is LOW, then data from the I/O pins is written into the location specified on the address pins. To read from the device, take Chip Enables and Output Enable LOW while forcing the Write Enable HIGH. If Byte Low Enable is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable is LOW, then data from memory appears on I/O8 to I/O15.

• TSOP I package configurable as 1 M × 16 or 2 M × 8 SRAM
• Very high speed: 45 ns
• Temperature ranges
  • Industrial: -40 °C to +85 °C
  • Automotive-A: -40 °C to +85 °C
• Wide voltage range: 2.20 V to 3.60 V
• Ultra-low standby power
  • Typical standby current: 1.5 ?A
  • Maximum standby current: 12 ?A
• Ultra-low active power
  • Typical active current: 2.2 mA at f = 1 MHz
• Easy memory expansion with CE1, CE2, and OE Features
• Automatic power-down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 48-ball VFBGA and 48-pin TSOP I packages