SRAM Chip Async Single 3.3V 4M-Bit 256K x 16 70ns 44-Pin TSOP-II

The IS65WV25616BLL are high speed, low power, 4M bit SRAMs organized as 256K words by 16 bits. It is fabricated using high-performance CMOS technology .This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. . When CS1\ is HIGH (deselected) or when CS1\ is low, and both LB\ and UB\ are HIGH, the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. . Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable(WE/) controls both writing and reading of the memory. A data byte allows Upper Byte (UB\) and Lower Byte (LB/) access. . The IS65WV25616BLL are packaged in the JEDEC standard 44-Pin TSOP (TYPE II) and 48-pin mini BGA (6mmx8mm).

• High-speed access time: 55ns, 70ns
• CMOS low power operation 36 mW (typical) operating 9 µW (typical) CMOS standby
• TTL compatible interface levels
• Single power supply: 2.5V-3.6V Vdd
• Fully static operation: no Clock or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Temperature offering
  • A1: -40°C to +85°C
  • A3: -40°C to +125°C
• Lead-free available