SRAM Chip Async Dual 5V 32K-Bit 4K x 8 25ns 68-Pin PLCC

The CY7C138 is a high-speed CMOS 4K x 8 and 4K x 9 dual-port static RAMs. Various arbitration schemes are included on the CY7C138 to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138 can be utilized as a standalone 8/9-bit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin. The CY7C138 are available in a 68-pin PLCC.

• True Dual-Ported memory cells which allow simultaneous reads of the same memory location
• 4K x 8 organization (CY7C138)
• 4K x 9 organization (CY7C139)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC