DSP 24-Bit 100MHz 100MIPS 196-Pin MA-BGA T/R

The DSP56303 is intended for use in telecommunication applications, such as multi-line voice/data/fax processing, videoconferencing, audio applications, control, and general digital signal processing. The DSP56303 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors (DSPs). This family uses a high performance, single clock cycle per instruction engine providing a twofold performance increase over Freescale"s popular DSP56000 core family, while retaining code compatibility. Significant architectural enhancements to the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The DSP56303 offers 100 MMACS using an internal 100 MHz clock at 3.0-3.6 volts. The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation, enabling a new generation of wireless, telecommunications, and multimedia products.

100 million multiply-accumulates per second (MMACS) with a 100 MHz clock

Object code compatible with the DSP56000 core

Highly parallel instruction set

Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)

56-bit parallel barrel shifter

24-bit or 16-bit arithmetic support under software control

Position-independent code support

Addressing modes optimized for DSP applications

On-chip instruction cache controller

On-chip memory-expandable hardware stack

Nested hardware DO loops

Fast auto-return interrupts

On-chip concurrent six-channel DMA controller

On-chip phase-lock loop (PLL) and clock generator

On-chip emulation (OnCE) module

JTAG test access port (TAP)

Address Tracing mode reflects internal accesses at the external port

Program RAM, instruction cache, X data RAM, and Y data RAM size is programmable:

192 x 24-bit bootstrap ROM

Data memory expansion to two 256 K x 24-bit word memory spaces

Program memory expansion to one 256 K x 24-bit word memory space

External memory expansion port

Chip select logic requires no additional circuitry to interface to SRAMs and SSRAMs

On-chip DRAM controller requires no additional circuitry to interface to DRAMs

8-bit parallel host interface (HI08), ISA-compatible bus interface, providing a cost-effective solution for applications not requiring the PCI bus

Two enhanced synchronous serial interfaces (ESSI)

Serial communications interface (SCI) with baud rate generator

Triple timer module

Up to thirty-four programmable general-purpose I/O pins (GPIO), depending on which peripherals are enabled

Very low power CMOS design

Wait and Stop low power standby modes

Fully-static logic, operation frequency down to DC

Optimized power management circuitry