DRAM Chip RLDRAM 576M-Bit 16Mx36 1.8V 144-Pin M-BGA Tray

RLDRAM 2 is a high-speed memory device designed for high bandwidth data storage, telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high-speed operation. The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output data is referenced to the free-running output data clock. Commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data clock(s). Read and write accesses are burst-oriented. The burst length (BL) is programmable from 2, 4, or 8 by setting the mode register. The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers. Bank-scheduled refresh is supported with the row address generated internally. The µBGA 144-ball package enables ultra high-speed data transfer rates and a simple upgrade path from early generation devices.

• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)
• Organization
• o64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O
• o8 banks
• Reduced cycle time (15ns at 533 MHz)
• Nonmultiplexed addresses (address multiplexing option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time, and burst sequence length
• Balanced READ and WRITE latencies in order to optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-die DLL generates CK edge-aligned data and output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms)
• HSTL I/O (1.5V or 1.8V nominal)
• 25–60O matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT