The STM8AF526x/8x/Ax and STM8AF6269/8x/Ax automotive 8-bit microcontrollers described in this datasheet offer from 32 Kbyte to 128 Kbyte of non volatile memory and integrated true data EEPROM. They are referred to as high density STM8A devices in STM8S series and STM8AF series 8-bit microcontrollers reference manual (RM0016).The STM8AF52 series features a CAN interface.All devices of the STM8A product line provide the following benefits: reduced system cost, performance and robustness, short development cycles, and product longevity.The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write/erase cycles and a high system integration level with internal clock oscillators, wtachdog, and brown-out reset.Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I/O, independent watchdogs (with a separate clock source), and a clock security system.
Core
Max fCPU: 24 MHz
Advanced STM8A core with Harvard architecture and 3-stage pipeline
Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPUfor industry standard benchmark
Memories
Program memory: 32 to 128 Kbyte Flash program; data retention 20 years at 55 °C
Data memory: up to 2 Kbyte true data EEPROM; endurance 300 kcycle
RAM: 6 Kbyte
Clock management
Low-power crystal resonator oscillator with external clock input
Internal, user-trimmable 16 MHz RC and low-power 128 kHz RC oscillators
Clock security system with clock monitor
Reset and supply management
Wait/auto-wakeup/Halt low-power modes with user definable clock gating
Low consumption power-on and power-down reset
Interrupt management
Nested interrupt controller with 32 vectors
Up to 37 external interrupts on 5 vectors
Timers
2 general purpose 16-bit timers with up to 3 CAPCOM channels each (IC, OC, PWM)
Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
8-bit AR basic timer with 8-bit prescaler
Auto-wakeup timer
Window and independent watchdog timers
I/Os
Up to 68 user pins (11 high sink I/Os)
Highly robust I/O design, immune against current injection
Communication interfaces
High speed 1 Mbit/s CAN 2.0B interface
USART with clock output for synchronous operation – LIN master mode
LINUART LIN 2.2 compliant, master/slave modes with automatic resynchronization
SPI interface up to 10 Mbit/s or fMASTER/2
I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit resolution, 2 LSB TUE, 1 LSB linearity and up to 16 multiplexed channels
Operating temperature up to 150 °C
Qualification conforms to AEC-Q100 grade 0
