SRAM Chip Sync Single 3.3V 9M-Bit 256K x 36-Bit 3.2ns 165-Pin FBGA Tray

The CY7C1354D is 3.3 V, 256 K × 36 synchronous pipelined burst SRAM with No Bus Latency (NoBLä) logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1354D are equipped with the advanced (NoBL) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. This feature greatly improves the throughput of data in systems that require frequent write/read transitions. The CY7C1354D are pin compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle.

• Pin-compatible and functionally equivalent to ZBT
• Supports 200 MHz bus operations with zero wait states
• Available speed grade is 200 MHz
• Internally self-timed output buffer control to eliminate the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined operation
• Byte write capability
• Single 3.3 V power supply (VDD)
• 3.3 V or 2.5 V I/O power supply (VDDQ)
• Fast clock-to-output times
• 3.2 ns (for 200 MHz device)
• Clock enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in non Pb-free 165-ball FBGA package
• IEEE 1149.1 JTAG-compatible boundary scan
• Burst capability - linear or interleaved burst order
• “ZZ” sleep mode option and stop clock option