SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 8ns 165-Pin FBGA Tray

The CY7C13451G is a 128 K × 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 8.0 ns (100 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input. The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable, depth expansion Chip Enables, Burst Control inputs, Write Enables, and Global Write. Asynchronous inputs include the Output Enable and the ZZ pin. The CY7C13451G enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses are initiated with the Processor Address Strobe or the cache Controller Address Strobe inputs. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor or Address Strobe Controller is active. Subsequent burst addresses are internally generated as controlled by the Advance pin. The CY7C13451G operates from a +3.3V core power supply while all outputs operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible.

• 128 K × 36 common I/O
• 3.3 V core Power Supply (VDD)
• 2.5 V or 3.3 V I/O Supply (VDDQ)
• Fast Clock-to-output times
  • 8.0 ns (100 MHz version)
• Provide high performance 2-1-1-1 access rate
• User selectable burst counter supporting Intel Pentium interleaved or Linear Burst Sequences
• Separate Processor and Controller Address Strobes
• Synchronous Self Timed Write
• Asynchronous output enable
• Available in Pb-free 165-ball FBGA Package
• ZZ Sleep Mode option