SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 8ns 100-Pin TQFP Tray

The GS840FH36AGT is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. The GS840FH36AGT is available in a JEDEC-standard 100-lead TQFP package.Controls :Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Designing For Compatibility :The JEDEC standard for Burst RAMs calls for a FT mode pin option (Pin 14 on TQFP). Board sites for flow through Burst RAMs should be designed with VSS connected to the FT pin location to ensure the broadest access to multiple vendor sources. Boards designed with FT pin pads tied low may be stuffed with GSI’s pipeline/flow through-configurable Burst RAMs or any vendor’s flow through or configurable Burst SRAM. Bumps designed with the FT pin location tied high or floating must employ a non-configurable flow through Burst RAM, (e.g., GS840FH36AGT), to achieve flow through functionality.Byte Write and Global Write :Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write control inputs.Sleep Mode :Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface Voltages :The GS840FH36AGT operates on a 3.3 V power supply and all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.

• Flow Through mode operation
• 3.3 V +10%/-5% core power supply
• 2.5 V or 3.3 V I/O supply
• NOT LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (NOT BW) and/or Global Write (NOT GW) operation
• Common data inputs and data outputs
• Clock Control, registered, address, data, and control
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP
• RoHS-compliant 100-lead TQFP package available