SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 2.6ns 100-Pin TQFP T/R

The 18 Meg NLP product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, "no wait" state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI"s advanced CMOS technology. Incorporating a "no wait" state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.

• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address, data and control
• Interleaved or linear burst sequence control using MODE input
• Three chip enables for simple depth expansion and address pipelining
• Power Down mode
• Common data inputs and data outputs
• CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball PBGA and 209-ball (x72) PBGA packages
• Power supply: VDD 3.3V (± 5%), VDDQ3.3V/2.5V (± 5%)
• JTAG Boundary Scan for PBGA packages
• Industrial temperature available
• Lead-free available
• Leaded option available upon request