SRAM Chip Sync Dual 1.8V/2.5V 9M-Bit 512K x 18 6.5ns/3ns 165-Pin FBGA Tray
SRAM Chip Sync Dual 1.8V/2.5V 9M-Bit 512K x 18 6.5ns/3ns 165-Pin FBGA Tray
- FT pin for user-configurable flow through or pipeline operation
- Single/Dual Cycle Deselect selectable
- IEEE 1149.1 JTAG-compatible Boundary Scan
- On-chip read parity checking; even or odd selectable
- ZQ mode pin for user-selectable high/low output drive
- 2.5 V or 3.3 V +10%/–10% core power supply
- 2.5 V or 3.3 V I/O supply
- LBO pin for Linear or Interleaved Burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to SCD x18/x36 Interleaved Pipeline mode
- Byte Write (BW) and/or Global Write (GW) operation
- Internal self-timed write cycle
- Automatic power-down for portable applications
- JEDEC-standard 119- and 165-bump BGA packages
- 4th Generation, Green 13 mm x 15 mm, 165 FPBGA
Характеристики
| Бренд | GSI Technology |
|---|---|
| Datasheet | |
| Timing Type | Synchronous |
| Number Of Words | 512 kWords |
| Density | 9 Mbit |
| Рабочая температура | 0 to 70 °C |
| Pin Count | 165 |
| Number Of Ports | 2 |
| Mounting | Surface Mount |
| Number Of | 18 Bit |
| Описание продукта | 15 x 13 x 0.94 mm |
| Typical O | 1.8, 2.5 V |
| ECCN | 3A991.B.2.B |
| Schedule B | 8542320040 |
| HTSN | 8542320041 |
| Страна происхождения | Taiwan |
| Minimum O | 1.7, 2.3 V |
| Maximum O | 2, 2.7 V |
| Data Rate | SDR |
| Architecture | Flow-Through|Pipelined |
| Lead Finish | Tin/Silver/Copper |
SKU: GS88218CGD-200V