SRAM Chip Sync Dual 1.8V/2.5V 36M-Bit 2M x 18 6.5ns/3ns 100-Pin TQFP Tray

The GS8320E18/32/36T-xxxV is a 37, 748, 736-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.Controls.Addresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV . The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used . New addresses can be loaded on every cycle with no degradation of chip performance.DCD Pipelined Reads.The GS8320E18/32/36T-xxxV is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.Byte Write and Global Write.Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.Sleep Mode.Low power (Sleep mode) is attained through the assertion (high) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface Voltages.The GS8320E18/32/36T-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (V DDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible.

• FT pin for user-configurable flow through or pipeline operation
• Single Dual Cycle Deselect (SDCD) operation
• 1.8 V or 2.5 V core power supply
• 1.8 V or 2.5 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package
• RoHS-compliant 100-lead TQFP package available
• Green TQFP