SRAM Chip Async Single 5V 4K-Bit 1K x 4-Bit 15ns 24-Pin PDIP

The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and data-acquisition applications. The CY7C150 has a memory reset feature that allows the entire memory to be reset in two memory cycles. Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable (OE) is held HIGH, allowing for easy memory expansion. Reset is initiated by selecting the device (CS = LOW) and taking the reset (RS) input LOW. Within two memory cycles all bits are internally cleared to zero. Since chip select must be LOW for the device to be reset, a global reset signal can be employed, with only selected devices being cleared at any given time. Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the four data inputs (D0-D3) is written into the memory location specified on the address pins (A0 through A9). Reading the device is accomplished by taking chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O0 through O3). The output pins remain in high-impedance state when chip enable (CE) or output enable (OE) is HIGH, or write enable (WE) or reset (RS) is LOW. A die coat is used to insure alpha immunity.

• Memory reset function
• 1024 x 4 static RAM for control store in high-speed computers
• CMOS for optimum speed/power
• High speed
  • 10 ns (commercial)
  • 12 ns (military)
• Low power
  • 495 mW (commercial)
  • 550 mW (military)
• Separate inputs and outputs
• 5-volt power supply ±10% tolerance in both commercial and military
• Capable of withstanding greater than 2001V static discharge
• TTL-compatible inputs and outputs