SRAM Chip Async Dual 3.3V 1M-Bit 128K x 8 25ns 100-Pin TQFP

The CY7C009V is a low-power CMOS 64 K, 128 K × 8 dual-port static RAM. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM.

• True dual-ported memory cells which allow simultaneous access of the same memory location
• 128 K × 8 organization (CY7C009)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
  • Active: ICC = 115 mA (typical)
  • Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16 bits or more using Master/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking between ports
• INT/ flag for port-to-port communication
• Dual chip enables
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
• Pb-free packages available