PHY 4-CH 289-Pin BGA

The TLK3104SA is a flexible four-channel serial backplane transceiver, delivering high-speed bidirectional point-to-point data transmissions to provide up to 10 Gbps of full duplex data transmission capacity. The TLK3104SA supports a broad operating range of serial data rates from 2.5 Gbps to 3.125 Gbps. The primary application of this device is to provide building blocks for developing point-to-point baseband data transmission over controlled impedance media of approximately 50 O. The transmission media can be printed-circuit-board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines. The TLK3104SA performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3104SA also provides a selectable 8-bit/10-bit (8b/10b) encode/decode function. The serial transmitter and receiver is implemented using differential pseudo-emitter coupled logic (PECL) compatible signaling called voltage mode logic (VML) that eliminates the need for external components. The four transceivers in the TLK3104SA can be configured as either four separate links, or synchronized together as a single data path. The TLK3104SA supports both the 32-bit data path, 4-bit control, 10 gigabit media independent interface (XGMII) and the extended auxiliary unit interface (XAUI) currently proposed in the IEEE 802.3ae 10 gigabit ethernet task force. Figure 1 shows an example system block diagram for the TLK3104SA used as an XGMII extended sublayer (XGXS) device to provide an additional trace distance on PCB for data being transferred between the switching fabric and optical transceiver modules.

Quad 3.125 Gbps per Channel Transceiver Providing 10 Gbps Data Throughput

Selectable Synchronized or Independent Channel Operation

Selectable Transmitter Only, Receiver Only, or Transceiver Functions

Selectable On-Chip 8-Bit/10-Bit Encoding/Decoding (ENDEC)

Supports IEEE 802.3ae Proposed XGMII Parallel Interface

Supports IEEE 802.3ae Proposed XAUI Serial Interface

Receiver Differential Input Thresholds 200-mV

On-Chip 100O Differential Receiver Termination

No External Filter Capacitors Required

PECL-Compatible Differential Signaling Serial Interface Using Voltage Mode Logic (VML) Driver

Auto-Selects Between 1.8-V HSTL or SSTL_2 Class 1 I/O With On-Chip 50O Series Termination on Outputs

Able to Operate With a Single 2.5-V Power Supply

On-Chip Pseudo-Random Bit Stream (PRBS) Generation and Verification for Self-Test

IEEE 802.3 Management Data Input/Output (MDIO) Interface

IEEE 1149.1 JTAG Test Interface

Hot Plug Protection

Mainstream 250 nm CMOS Technology

Small Footprint 19×19 mm 289 Ball PBGA Package