PHY 2-CH 1Gbps 48-Pin QFN Tray

The Intel® Ethernet Connection I218 is a single-port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to an integrated Media Access Controller (MAC) through a dedicated interconnect. The Intel® Ethernet Connection I218 supports operation at 1000/100/10 Mb/s data rates. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The Intel® Ethernet Connection I218 also supports the Energy Efficient Ethernet (EEE) 802.az specification.

• General
  • 10 BASE-T IEEE 802.3 specification conformance
  • 100 BASE-TX IEEE 802.3 specification conformance
  • 1000 BASE-T IEEE 802.3 specification conformance Energy Efficient Ethernet (EEE) IEEE 802.3az support [Low Power Idle (LPI) mode]
  • IEEE 802.3u auto-negotiation conformance
  • Supports carrier extension (half duplex)
  • Loopback modes for diagnostics
  • Advanced digital baseline wander correction
  • Automatic MDI/MDIX crossover at all speeds of operation
  • Automatic polarity correction
  • MDC/MDIO management interface
  • Flexible filters in PHY to reduce integrated LAN controller power
  • Smart speed operation for automatic speed reduction on faulty cable plants
  • PMA loopback capable (no echo cancel)
  • 802.1as/1588 conformance
  • Power Optimizer Support
  • Intel® Stable Image Platform Program (SIPP)
  • iSCSI Boot
  • Network proxy/ARP Offload support
  • Up to 16 programmable filters
• Security & Manageability
  • Intel® vPro support with appropriate Intel chipset components
• Performance
  • Jumbo Frames (up to 9 kB)
  • 802.1Q & 802.1p
  • Receive Side Scaling (RSS)
  • Two Queues (Tx & Rx)
• Power
  • Ultra Low Power at cable disconnect (<1 mW) enables platform support for connected standby
  • Reduced power consumption during normal operation and power down modes
  • Integrated Intel® Auto Connect Battery Saver (ACBS)
  • Single-pin LAN Disable for easier BIOS implementation
  • Fully integrated Switching Voltage Regulator (iSVR)
  • Low Power LinkUp (LPLU)
• MAC/PHY Interconnect
  • PCIe-based interface for active state operation (S0 state)
  • SMBus-based interface for host and management traffic (Sx low power state)
• Package/Design
  • 48-pin package, 6 x 6 mm with a 0.4 mm lead pitch and an Exposed Pad for ground
  • Three configurable LED outputs
  • Integrated MDI interface termination resistors to reduce BOM costs
  • Reduced BOM cost by sharing SPI flash with PCH