PHY 2-CH 195Mbps/1.5Gbps 256-Pin BGA

The CYV15G0203TB Independent Clock Dual HOTLink II Serializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The two channels are independent and can simultaneously operate at different rates. Each channel accepts 10-bit parallel characters in an Input Register and converts them to serial data. Figure 1 illustrates typical connections between independent video co-processors and corresponding CYV15G0203TB Serializer and CYV15G0204RB Reclocking Deserializer chips. The CYV15G0203TB satisfies the SMPTE-259M and SMPTE-292M compliance as per SMPTE EG34-1999 Pathological Test Requirements. As a second-generation HOTLink device, the CYV15G0203TB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data, and BIST) with other HOTLink devices. Each channel of the CYV15G0203TB Dual HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from dual Positive ECL (PECL) compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. Each channel contains an independent BIST pattern generator. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit section of this device, each receive section of a connected HOTLink II device, and across the interconnecting links. The CYV15G0203TB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, and cameras.

• Second-generation HOTLink® technology
• Compliant to SMPTE 292M and SMPTE 259M video standards
• Dual-channel video serializer
• 195- to 1500-Mbps serial data signaling rate
• Simultaneous operation at different signaling rates
• Supports half-rate and full-rate clocking
• Internal phase-locked loops (PLLs) with no external PLL components
• Redundant differential PECL-compatible serial outputs per channel
• No external bias resistors required
• Signaling-rate controlled edge-rates
• Internal source termination
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
• Low-power 1.4 W @ 3.3 V typical
• Single 3.3 V supply
• Thermally enhanced BGA
• Pb-free package option available
• 0.25 BiCMOS technology