PHY 1-CH 270Mbps/360Mbps 28-Pin PLCC

The CY7B9234 SMPTE HOTLink Transmitter and CY7B9334 SMPTE HOTLink Receiver bolt on to the SMPTE Scrambler Controller (CY7C9235) and SMPTE Descrambler/Framer Controller (CY7C9335) completing the four piece chipset to transfer uncompressed SMPTE-259M encoded video over high-speed serial links (fiber, coax, and twisted pair). SMPTE HOTLink supports SMPTE-259M-CD standard data rates at 270 and 360 Mbps. Figure 1 illustrates typical connections to host systems or controllers. Eight or ten bits of user data or protocol information are loaded into the SMPTE HOTLink transmitter and, in DVB mode, are encoded. Serial data is shifted out of the three differential positive ECL (PECL) serial ports at the bit rate (which is 10 times the byte rate). The SMPTE HOTLink receiver accepts the serial bit stream at its differential line receiver inputs and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The bit stream is deserialized, and in DVB mode, decoded and checked for transmission errors. Recovered bytes are presented in parallel to the receiving host along with a byte rate clock. The 8B/10B encoder/decoder can be disabled in SMPTE or DVB systems that already encode or scramble the transmitted data. I/O signals are available to create a seamless interface with both asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e., CY7C44X). A Built-In Self-Test pattern generator and checker allows testing of the transmitter, receiver, and the connecting link as a part of a system diagnostic check. SMPTE HOTLink devices are ideal for a variety of video applications including video transmission equipment, video recorders, video editing equipment, and video routers.

• SMPTE-259M-CD compliant along with SMPTE-259M encoder (CY7C9235) and decoder (CY7C9335)
• Fibre Channel compliant
• DVB-ASI compliant
• RX PLL tolerant of long run length data patterns (>20 bits)
• 8B/10B-coded or 10-bit unencoded
• TTL synchronous I/O
• No external PLL components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and twisted pair media
• Built-In Self-Test
• Single +5V supply
• 28-pin PLCC
• 0.8µ BiCMOS