PHY 1-CH 10Mbps/100Mbps/1Gbps 48-Pin QFN EP

The 82577 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the Intel 5 Series Express Chipset integrated Media Access Controller (MAC) through a dedicated interconnect. The 82577 supports operation at 1000/100/ 10 Mb/s data rates. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The 82577 is packaged in a small footprint QFN package. Package size is 6 x 6 mm with a 0.4 mm lead pitch and a height of 0.85 mm, making it very attractive for small formfactor platforms. The 82577 interfaces with its MAC through two interfaces: PCIe-based and SMBus. The PCIe (main) interface is used for all link speeds when the system is in an active state (S0) while the SMBus is used only when the system is in a low power state (Sx). In SMBus mode, the link speed is reduced to 10 Mb/s (dependent on low power options). The PCIe interface incorporates two aspects: a PCIe SerDes (electrically) and a custom logic protocol.

• General
  • 10/100/1000 BASE-T IEEE 802.3 specification conformance
  • Integrated MDI interface termination resistors to reduce BOM costs
  • Supports up to 4 KB jumbo frames (full duplex)1
  • Supports carrier extension (half duplex)
  • Energy detect low power modes
  • Loopback modes for diagnostics
  • Fully integrated digital adaptive equalizers, echo cancellers, and crosstalk cancellers
  • Advanced digital baseline wander correction
  • Automatic MDI/MDIX crossover at all speeds of operation
  • Automatic polarity correction
  • IEEE 802.3u auto-negotiation conformance
  • MDC/MDIO management interface
  • Flexible filters in PHY to reduce MAC power
  • Shared NVM access through the MAC
  • MACSec hardware ready (802.1AE), Intel® VPro, Intel® Viiv and Virtualization support with appropriate Intel® chipset(s) components
  • Smart speed operation for automatic speed reduction on faulty cable plants
  • PMA loopback capable (no echo cancel).
• Advanced cable diagnostics
  • TDR
  • Channel frequency response
• Extended configuration load sequence
• Power
  • Reduced power consumption during normal operation and power down modes
  • Integrated Intel® Auto Connect Battery Saver
  • Single pin LAN Disable for easier BIOS implementation
• Dual interconnect between the Media Access Controller (MAC)2 and Physical Layer (PHY):
  • PCIe-based interface for active state operation (S0 state)
  • SMBus for host and management traffic (Sx low power state)
• Technology
  • 48-pin package, 6 x 6 mm with a 0.4 mm lead pitch and an Exposed Pad for ground
  • Three configurable LED outputs
  • Flexible power configuration: use either the Intel® 5 Series Express Chipset 1.05 Vdc shared voltage rail or the fully integrated 82577 1.0 Vdc linear regulation