The medium-density STM8AL313x/4x/6x and STM8AL3L4x/6x devices are members of the STM8AL automotive ultra-low-power 8-bit family. The medium-density STM8AL3xxx family operates from 1.8 V to 3.6 V (down to 1.65 V at power down) and is available in the -40 to +85°C and -40 to +125°C temperature ranges.The medium-density STM8AL3xxx ultra-low-power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultrafast Flash programming.All medium-density STM8AL3xxx microcontrollers feature embedded data EEPROM and low power low-voltage single-supply program Flash memory.They incorporate an extensive range of enhanced I/Os and peripherals.The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.Two different packages are proposed which include 32 and 48 pins. Depending on the device chosen, different sets of peripherals are included.All STM8AL3xxx ultra-low-power products are based on the same architecture with the same memory mapping and a coherent pinout.
Operating conditions
Operating power supply range 1.8 V to 3.6 V (down to 1.65 V at power down)
Temperature range: – 40 °C to 85 or 125 °C
Low power features
Five low-power modes: Wait, low-power run (5.1 µA), low-power wait (3 µA), active-halt with full RTC (1.3 µA), halt with PDR (400 nA)
Run from Flash: 195 µA/MHz + 440 µA
Run from RAM: 90 µA/MHz + 400 µA
Ultra-low leakage per I/0: 50 nA
Fast wakeup from Halt: 4.7 µs
Advanced STM8 core
Harvard architecture and 3-stage pipeline
Max freq. 16 MHz, 16 CISC MIPS peak
Up to 40 external interrupt sources
Reset and supply management
Low power, ultra safe BOR reset with 5 selectable thresholds
Ultra-low power POR/PDR
Programmable voltage detector (PVD)
Clock management
1 to 16 MHz crystal oscillator
32 kHz crystal oscillator
Internal 16 MHz factory-trimmed RC
Internal 38 kHz low consumption RC
Clock security system
Low power RTC
BCD calendar with alarm interrupt
Auto-wakeup from Halt (0.95 ppm resolution) w/ periodic interrupt
LCD: up to 4×28 segments w/ step-up converter
Memories
Program memory: up to 32 Kbyte Flash program; data retention 20 years at 55 °C
Data memory: up to 1 Kbyte true data EEPROM; endurance 300 kcycle
RAM: up to 2 Kbyte
DMA
Four channels; supported peripherals: ADC, DAC, SPI, I2C, USART, timers
One channel for memory-to-memory
12-bit DAC with output buffer
12-bit ADC up to 1 Mbps/25 channels
Temp sensor and internal reference voltage
Two ultra-low-power comparators
One with fixed threshold and one rail to rail
Wakeup capability
Timers
Two 16-bit timers with two channels (used as IC, OC, PWM), quadrature encoder
One 16-bit advanced control timer with three channels, supporting motor control
One 8-bit timer with 7-bit prescaler
Two watchdogs: one window, one independent
Beeper timer with 1-, 2- or 4 kHz frequencies
Communication interfaces
Synchronous serial interface (SPI)
Fast I2C 400 kHz SMBus and PMBus
USART (ISO 7816 interface, IrDA, LIN 1.3, LIN 2.0)
Up to 41 I/Os, all mappable on interrupt vectors
Development support
Fast on-chip programming and non intrusive debugging with SWIM
Bootloader using USART
96-bit unique ID
AEC-Q100 grade 1 conform qualification
