Описание
The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture, as illustrated in the “Logic Block Diagram” on page 1, comprises of four main areas: the core, the system resources, the digital system, and the analog system. Configurable global bus resources allow all the device resources to be combined into a complete custom system. Each CY8C21x12 device includes one limited digital block and one CapSense block. Depending on the PSoC package, up to 24 GPIOs are also included. The GPIOs provide access to the global digital and analog interconnects.
- Powerful Harvard-architecture processor
- M8C processor speeds up to 24 MHz
- 8 × 8 multiply, 32-bit accumulate
- Low power at high speed
- Operating voltage: 3.0 V to 5.25 V
- Operating voltages down to 1.0 V using on-chip switch mode pump (SMP)
- Industrial temperature range: -40 ?C to +85 ?C
- Advanced peripherals (PSoC® blocks)
- Tweleve rail-to-rail analog PSoC blocks provide:
- Up to 14-bit analog-to-digital converters (ADCs)
- Up to 9-bit digital-to-analog converters (DACs)
- Programmable gain amplifiers (PGAs)
- Programmable filters and comparators
- Eight digital PSoC blocks provide:
- 8- to 32-bit timers, counters, and pulse width modulators (PWMs)
- Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules
- Up to two full-duplex universal asynchronous receiver transmitters (UARTs)
- Multiple serial peripheral interface (SPI) masters or slaves
- Connectable to all general-purpose I/O (GPIO) pins
- Complex peripherals by combining blocks
- Precision, programmable clocking
- Internal 2.5% 24- / 48-MHz main oscillator
- 24- / 48-MHz with optional 32 kHz crystal
- Optional external oscillator up to 24 MHz
- Internal oscillator for watchdog and sleep
- Flexible on-chip memory
- 16 KB flash program storage 50,000 erase/write cycles
- 256-bytes SRAM data storage
- In-system serial programming (ISSP)
- Partial flash updates
- Flexible protection modes
- Electronically erasable programmable read only memory (EEPROM) emulation in flash
- Programmable pin configurations
- 25-mA sink, 10-mA source on all GPIOs
- Pull-up, pull-down, high-Z, strong, or open-drain drive modes on all GPIOs
- Eight standard analog inputs on GPIO, plus four additional analog inputs with restricted routing
- Four 30-mA analog outputs on GPIOs
- Configurable interrupt on all GPIOs
- Additional system resources
- I2C slave, master, and multi-master to 400 kHz
- Watchdog and sleep timers
- User-configurable low-voltage detection (LVD)
- Integrated supervisory circuit
- On-chip precision voltage reference
- Complete development tools
- Free development software (PSoC Designer™)
- Full-featured, in-circuit emulator (ICE) and programmer
- Full-speed emulation
- Complex breakpoint structure
- 128 KB trace memory
