Описание
The PSoC family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog blocks, digital blocks, and interconnections. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application.
- Varied resource options within one PSoC® device group
- Powerful Harvard-architecture processor
- M8C processor speeds up to 24 MHz
- 8 × 8 Multiply, 32-bit accumulate
- Low power at high speed
- Operating voltage: 3.0 V to 5.25 V
- Operating voltages down to 1.5 V Using on-chip switched mode pump (SMP)
- Industrial temperature range: -40 °C to +85 °C
- Advanced reconfigurable peripherals (PSoC Blocks)
- Up to 12 rail-to-rail analog PSoC blocks provide: Up to 14-bit ADCs, Up to 9-bit DACs, Programmable gain amplifiers, Programmable filters and comparators, Multiple ADC configurations, Dedicated SAR ADC, up to 142 ksps with sample and hold
- Up to 4 synchronized or independent delta-sigma ADCs for advanced applications
- Up to 4 limited type E analog blocks provide: Dual channel capacitive sensing capability, Comparators with programmable DAC reference, Up to 10-bit single-slope ADCs
- Up to 12 digital PSoC blocks provide: 8- to 32-bit timers and counters, 8- and 16-bit pulse-width modulators (PWMs), Shift register, CRC, and PRS modules, Up to 3 full-duplex UARTs, Multiple variable data length SPI™ masters or slaves, Connectable to all GPIOs
- Complex peripherals by combining blocks
- Precision, programmable clocking
- Internal ±2.5% 24/48 MHz main oscillator
- Optional 32.768 kHz crystal for precise on-chip clocks
- Optional external oscillator, up to 24 MHz
- Internal low speed, low power oscillator for watchdog and sleep functionality
- Flexible on-chip memory
- 16 KB flash program storage 50,000 erase/write cycles
- 1-KB SRAM data storage
- In-system serial programming (ISSP™)
- Partial flash updates
- Flexible protection modes
- EEPROM emulation in flash
- Programmable Pin configurations
- 25 mA sink, 10 mA drive on all GPIOs
- Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs
- Analog input on all GPIOs
- 30 mA analog outputs on GPIOs
- Configurable interrupt on all GPIOs
- Additional system resources
- Up to two hardware I2C resources: Each resource implements slave, master, or multi-master modes, Operation between 0 and 400 kHz
- Watchdog and Sleep timers
- User-configurable low voltage detection
- Flexible internal voltage references
- Integrated supervisory circuit
- On-chip precision voltage reference
