Description
PIC18F86J65 is new line of low-voltage devices with the foremost traditional advantage of all PIC18 microcontrollers – namely, high computational performance and a rich feature set at an extremely competitive price point. These features make the PIC18F97J60 family a logical choice for many high-performance applications where cost is a primary consideration. All of the devices in the PIC18F97J60 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These options include: Two Crystal modes, using crystals or ceramic resonators. Two External Clock modes, offering the option of a divide-by-4 clock output. A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes, which allows clock speeds of up to 41.667 MHz. An internal RC oscillator with a fixed 31 kHz output which provides an extremely low-power option for timing-insensitive applications. The internal oscillator block provides a stable reference source that gives the family additional features for robust operation: Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available The PIC18F97J60 family provides ample room for application code, from 64 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last 100 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The PIC18F97J60 family also provides plenty of room for dynamic application data with 3808 bytes of data RAM. In the unlikely event that 128 Kbytes of memory are inadequate for an application, the 100-pin members of the PIC18F97J60 family also implement an External Memory Bus (EMB). This allows the controller’s internal program counter to address a memory space of up to 2 Mbytes, permitting a level of data access that few 8-bit devices can claim. This allows additional memory options, including: Using combinations of on-chip and external memory up to the 2-Mbyte limit Using external Flash memory for reprogrammable application code or large data tables Using external RAM devices for storing large amounts of variable data The PIC18F97J60 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize reentrant application code originally developed in high-level languages, such as C. Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve.
- Ethernet Features: IEEE 802.3™ Compatible Ethernet Controller
- Fully Compatible with 10/100/1000Base-T Networks
- Integrated MAC and 10Base-T PHY
- 8-Kbyte Transmit/Receive Packet Buffer SRAM
- Supports One 10Base-T Port
- Programmable Automatic Retransmit on Collision
- Programmable Padding and CRC Generation
- Programmable Automatic Rejection of Erroneous Packets
- Activity Outputs for 2 LED Indicators
- Buffer: Configurable transmit/receive buffer size
- Hardware-managed circular receive FIFO
- Byte-wide random and sequential access
- Internal DMA for fast memory copying
- Hardware assisted checksum calculation for various protocols
- MAC: Support for Unicast, Multicast and Broadcast packets
- Programmable Pattern Match of up to 64 bytes within packet at user-defined offset
- Programmable wake-up on multiple packet formats
- PHY: Wave shaping output filter
- Flexible Oscillator Structure:
- Selectable System Clock derived from Single
- 25 MHz External Source:
- 2.778 to 41.667 MHz
- Internal 31 kHz Oscillator
- Secondary Oscillator using Timer1 @ 32 kHz
- Fail-Safe Clock Monitor:
- Allows for safe shutdown if oscillator stops
- Two-Speed Oscillator Start-up External Memory Bus
- (100-pin devices only):
- Address Capability of up to 2 Mbytes
- 8-Bit or 16-Bit Interface
- 12-Bit, 16-Bit and 20-Bit Addressing modes
- Peripheral Highlights:
- High-Current Sink/Source: 25 mA/25 mA on PORTB and PORTC
- Five Timer modules (Timer0 to Timer4)
- Four External Interrupt pins
- Two Capture/Compare/PWM (CCP) modules
- Three Enhanced Capture/Compare/PWM (ECCP) modules:
- One, two or four PWM outputs
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
- Up to Two Master Synchronous Serial Port (MSSP) modules supporting SPI (all 4 modes) and I2C™ Master and Slave modes
- Up to Two Enhanced USART modules:
- Supports RS-485, RS-232 and LIN/J2602
- Auto-wake-up on Start bit
- Auto-Baud Detect (ABD)
- 10-Bit, Up to 16-Channel Analog-to-Digital Converter module (A/D):
- Auto-acquisition capability
- Conversion available during Sleep
- Dual Analog Comparators with Input Multiplexing
- Parallel Slave Port (PSP) module (100-pin devices only) Special Microcontroller Features:
- 5.5V Tolerant Inputs (digital-only pins)
- Low-Power, High-Speed CMOS Flash Technology:
- Self-reprogrammable under software control
- C compiler Optimized Architecture for Reentrant Code
- Power Management Features:
- Run: CPU on, peripherals on
- Idle: CPU off, peripherals on
- Sleep: CPU off, peripherals off
- Priority Levels for Interrupts
- 8 x 8 Single-Cycle Hardware Multiplier
- Extended Watchdog Timer (WDT):
- Programmable period from 4 ms to 134s
- Single-Supply 3.3V In-Circuit Serial Programming™ (ICSP™) via Two Pins
- In-Circuit Debug (ICD) with 3 Breakpoints via Two Pins
- Operating Voltage Range of 2.35V to 3.6V (3.1V to 3.6V using Ethernet module)
- On-Chip 2.5V Regulator
