Описание
The MN101E series of 8-bit single-chip microcompute rs (the memory expansion version of MN101C series) incorporate multiple types of peripheral functions. This chip series is well suited for automotive power window, camera, TV, CD, printer, telephone, home appliance, PPC, fax machine, music instrument and other applications. This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim- ple efficient instruction set. MN101EFA5 as an internal 32 KB of ROM and 1 KB of RAM. Periph- eral functions include 5 external in terrupts, including NMI, 8 timer counter s, 2 types of serial interfaces, A/D converter, watchdog timer and no buzzer. The system configuration is suitable for system control microcontroller With 2 oscillation systems (internal frequency: 16 MHz, crystal/ceramic frequency: max. 10 MHz) contained on the chip, the system clock can be switched to high- speed frequency input (NORMAL mode) or PLL input (PLL mode). The system clock is generated by dividing the osc illation clock or PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by programming. High speed mode has NORMAL mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2), and the double speed mode which is based on the clock not dividing fpll A machine cycle (minimum instruction execution time) in NORMAL mode is 200 ns when the original oscillation fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (maximum).
- ROM capacity: 32 KB
- RAM capacity: 1 KB
- Package: MN101EFA5
- 32-Pin TQFP (7 mm x 7 mm / 0.8mm pitch)
- 32-Pin SSOP (6.1 mm x 11 mm / 0.65mm pitch, halogen free)
- Machine Cycle:0.05 µs / fs: 20 MHz (4.0 V to 5.5 V)
- Oscillation circuit: 2 channel oscillation circuit
- Internal oscillation (frc): 16 MHz Crystal/ceramic (fosc): Maximum 10 MHz
- Clock Multiplication circuit (PLL Circuit)
- PLL circuit output clock (fpll): fosc multiplied by 2, 3, 4, 5, 6, 8, 10, 1/2 x frc multiplication by 4, 5 enable
- Clock Gear for System Clock
- System Clock (fs): fpll divided by 1, 2, 4, 16, 32, 64, 128
- Clock Gear for control clock of peripheral function
- Control clock of peripheral function (fpll-div): stop or fpll divided by 1, 2, 4, 8, 16
- Operation Mode:
- NORMAL mode
- HALT mode
- STOP mode (The operation clock can be switched in each mode.)
- Operating Voltage: 4.0 V to 5.5 V
- Interrupt:
- MN101EFA5: 25 levels
- A/D Converter: 10-bit x 8 channels
- Automatic Reset: Power detection level: 4.3 V (at rising), 4.2 V (at falling)
- LED Driver: 16 pins (Port 0 or Port A)
