Description
The Microchip AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The Microchip AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The AVR XMEGA A1U devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and programmable multilevel interrupt controller, 78 general purpose I/O lines, 16-bit real-time counter (RTC); eight flexible, 16-bit timer/counters with compare and PWM channels, eight USARTs; four two-wire serial interfaces (TWIs); one full speed USB 2.0 interface; four serial peripheral interfaces (SPIs); AES and DES cryptographic engine; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) generator; two 16-channel, 12-bit ADCs with programmable gain; two 2-channel, 12-bit DACs; four Analog Comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.
- High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
- Nonvolatile program and data memories
- 64K – 128KBytes of in-system self-programmable flash
- 4K – 8KBytes boot section
- 2KBytes EEPROM
- 4K – 8KBytes internal SRAM
- External bus interface for up to 16Mbytes SRAM
- External bus interface for up to 128Mbit SDRAM
- Peripheral features
- Four-channel DMA controller
- Eight-channel event system
- Eight 16-bit timer/counters
- Four timer/counters with 4 output compare or input capture channels
- Four timer/counters with 2 output compare or input capture channels
- High resolution extension on all timer/counters
- Advanced waveform extension (AWeX) on two timer/counters
- One USB device interface
- USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
- 32 Endpoints with full configuration flexibility
- Eight USARTs with IrDA support for one USART
- Four two-wire interfaces with dual address match (I2C and SMBus compatible)
- Four serial peripheral interfaces (SPIs)
- AES and DES crypto engine
- CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
- 16-bit real time counter (RTC) with separate oscillator
- Two sixteen channel, 12-bit, 2msps Analog to Digital Converters
- Two Two-channel, 12-bit, 1msps Digital to Analog Converters
- Four Analog Comparators (ACs) with window compare function, and current sources
- External interrupts on all general purpose I/O pins
- Programmable watchdog timer with separate on-chip ultra low power oscillator
- QTouch® library support
- Capacitive touch buttons, sliders and wheels
- Special microcontroller features
- Power-on reset and programmable brown-out detection
- Internal and external clock options with PLL and prescaler
- Programmable multilevel interrupt controller
- Five sleep modes
- Programming and debug interfaces
- JTAG (IEEE 1149.1 compliant) interface, including boundary scan
- PDI (Program and Debug Interface)
- I/O and packages
- 78 Programmable I/O pins.
