Описание
The TMPM332 is a 32-bit RISC microprocessor series with an ARM Cortex-M3 microprocessor core.
- ARM Cortex-M3 microprocessor core
- Improved code efficiency has been realized through the use of Thumb® -2 instruction
- New 16-bit Thumb instructions for improved program flow
- New 32-bit Thumb instructions for improved performance
- New Thumb mixed 16-/32-bit instruction set can produce faster, more efficient code
- Both high performance and low power consumption have been achieved.[High performance]
- A 32-bit multiplication (32×32=32 bit) can be executed with one clock
- Division takes between 2 and 12 cycles depending on dividend and devisor[Low power consumption]
- Optimized design using a low power consumption library
- Standby function that stops the operation of the micro controller core
- High-speed interrupt response suitable for real-time control
- An interruptible long instruction
- Stack push automatically handled by hardware.
- 16-bit timer (TMRB): 10 channels
- 16-bit interval timer mode
- 16-bit event counter mode
- 16-bit PPG output
- Input capture function
- Real time clock (RTC): 1 channel
- Clock (hour, minute and second)
- Calendar (month, week, date and leap year)
- Time correction + or – 30seconds (by software)
- Alarm (Alarm output)
- Alarm interrupt
- Watchdog timer (WDT): 1 channelWatchdog timer (WDT) generates a reset or a non-maskable interrupt (NMI).
- General-purpose serial interface (SIO/UART): 2 channels
- Either UART mode or synchronous mode can be selected (4byte FIFO equipped)
- Serial bus interface (I²C/SIO): 2channels
- Either I²C bus mode or synchronous mode can be selected.
- CEC function (CEC): 1 channel
- Transmission and reception per 1 byte.
- Remote control signal preprocessor (RMC): 1 channels
- Can receive up to 72bit data at a time
- 10-bit AD converter (ADC): 8 channels
- Start by an internal timer trigger
- Fixed channel/scan mode
- Single/repeat mode
- AD monitoring 2ch
- Conversion speed 1.15µsec. (@fsys = 40MHz)
- Interrupt source
- Internal: 32 factors..The order of precedence can be set over 7 levels(except the watchdog timer interrupt)
- External: 5 factors..The order of precedence can be set over 7 levels.
- Non-maskable interrupt (NMI)
- Non-maskable interrupt (NMI) is generated by a watchdog timer or a NMI pin.
