Description
The SH7616 is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an original Renesas architecture with supporting functions required for an Ethernet system.The CPU has a RISC (Reduced Instruction Set Computer) type instruction set. The CPU basically operates at a rate of one instruction per cycle, offering a great improvement in instruction execution speed. In addition, the 32-bit internal architecture provides improved data processing power, and DSP functions have also been enhanced with the implementation of extended Harvard architecture DSP data bus functions. With this CPU, it has become possible to assemble low-cost, high-performance/high-functionality systems even for applications such as real time control, which could not previously be handled by microcontrollers because of their high-speed processing requirements. The SH7616 also includes a maximum 4-kbyte cache, for greater CPU processing power when accessing external memory.The SH7616 is equipped with a media access controller (MAC) conforming to the IEEE802.3u standard, and an Ethernet controller that includes a media independent interface (MII) standard unit, enabling 10/100 Mbps LAN connection. Supporting functions necessary for system configuration are also provided, including RAM, timers, a serial communication interface with FIFO (SCIF), interrupt controller (INTC), and I/O ports.To improve the efficiency of frame transmission/reception, the processing power of the DMAC for the Ethernet controller is improved and the FIFO for the DMAC has 2 kbytes. A CAM match signal input function is provided for systems that require multiple MAC addresses. In serial I/O with three channels, one operates with the FIFO for better data processing power when connected to the codec.
- Original Renesas architecture
- 32-bit internal architecture
- General register machine
- Sixteen 32-bit general registers
- Six 32-bit control registers (including 3 added for DSP use)
- Ten 32-bit system registers
- RISC (Reduced Instruction Set Computer) type instruction set
- Fixed 16-bit instruction length for improved code efficiency
- Load-store architecture (basic operations are executed between registers)
- Delayed branch instructions reduce pipeline disruption during branches
- C-oriented instruction set
- Instruction execution time: One instruction per cycle (16.0 ns/instruction at 62.5 MHz operation)
- Address space: Architecture supports 4 Gbytes
- On-chip multiplier: Multiply operations (32 bits × 32 bits ? 64 bits) and multiply-and-accumulate operations (32 bits × 32 bits + 64 bits ? 64 bits) executed in two to four cycles
- Five-stage pipeline
