Description
This LSI is a microcomputer, featuring an LCD controller, USB host, and other peripheral functions. The SuperH RISC engine is a Renesas Technology-original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH RISC engine employs a fixed-length 16- bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit instruction set. This LSI features the SH-4 CPU, which at the instruction set level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. This LSI has an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry full-associative instruction TLB (translation look aside buffer), and MMU (memory management unit) with 64- entry full-associative shared TLB. The sizes of the instruction cache and operand cache are 16 Kbytes and 32 Kbytes. This LSI also features the bus state controller (BSC) that can connect to synchronous DRAM. Also, because of its on-chip functions, such as an LCD controller, a USB host, timers, and serial communication functions, required for multimedia and OA equipment, this LSI enables a dramatic reduction in system costs.
- Operating frequency: 200 MHz
- Performance: 360MIPS, 1.4 GFLOPS
- Voltage: 1.5 V (internal), 3.3 V (I/O)
- Superscalar architecture: Parallel execution of two instructions
- Packages: 256-pin BGA (Size: 17 × 17 mm, pin pitch: 0.8 mm)
- External buses:
- Separate 26-bit address and 32-bit data buses
- External bus frequency: 67MHz
- Choice of MFI mode or LCD mode:
- MFI mode: 8-/16-bit parallel interface (supports 68-/80-family interface)
- LCD mode: LCD controller/data output
- Original Renesas Technology SuperH architecture
- 32-bit internal data bus
- General register file:
- Sixteen 32-bit general registers (and eight 32-bit shadow registers)
- Seven 32-bit control registers
- Four 32-bit system registers
- RISC-type instruction set (upward-compatible with SH-1, SH-2, and SH-3)
- Fixed 16-bit instruction length for improved code efficiency
- Load-store architecture
- Delayed branch instructions
- Conditional execution
- C-based instruction set
- Superscalar architecture (providing simultaneous execution of two instructions) including FPU
- Instruction execution time: Maximum 2 instructions/cycle
- Virtual address space: 4 Gbytes (448-Mbyte external memory space)
- Space identifier ASIDs: 8 bits, 256 virtual address spaces
- On-chip multiplier
- 5-stage pipeline
- Instruction cache (IC)
- 16-Kbyte, 2-way set associative (LRU)
- 256 entries, 32-byte block length
- Cache-double-mode (16-Kbyte cache)
- Index mode
- Nine independent external interrupts: NMI, IRL3 to IRL0, and IRQ7 to IRQ4
- Supports external memory access
- 3-channel auto-reload 32-bit timer
- 8-channel physical address DMA controller
- Three full-duplex communications channels
