Description
The SH7751 Series microprocessor, featuring a built-in PCI bus controller compatible with PCs and multimedia devices. The SuperH RISC engine is a Hitachi-original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH RISC engine employs a fixed-length 16-bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit instruction set.The SH7751 Series feature the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751 Series have an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry full associative instruction TLB (table look aside buffer), and MMU (memory management unit) with 64-entry full-associative shared TLB.The SH7751 Series also feature a bus state controller (BSC) that can be directly coupled to DRAM (page/EDO) and synchronous DRAM without external circuitry. Also, because of its built-in functions, such as PCI bus controller, timers, and serial communications functions, required for multimedia and OA equipment, use of the SH7751 Series enable a dramatic reduction in system costs.
- Original Hitachi SuperH architecture
- 32-bit internal data bus
- General register file
- Sixteen 32-bit general registers (and eight 32-bit shadow registers)
- Seven 32-bit control registers
- Four 32-bit system registers
- RISC-type instruction set (upward-compatible with SuperH Series)
- Fixed 16-bit instruction length for improved code efficiency
- Load-store architecture
- Delayed branch instructions
- Conditional execution
- C-based instruction set
- Superscalar architecture (providing simultaneous execution of two instructions) including FPU
- Instruction execution time: Maximum 2 instructions/cycle
- Virtual address space: 4 Gbytes (448-Mbyte external memory space)
- Space identifier ASIDs: 8 bits, 256 virtual address spaces
- On-chip multiplier
- Five-stage pipeline
