Описание
STM32H750xB devices are based on the high-performance Arm Cortex-M7 32-bit RISC core operating at up to 400 MHz. The Cortex -M7 core features a floating point unit (FPU) which supports Arm double-precision (IEEE 754 compliant) and single-precision dataprocessing instructions and data types. STM32H750xB devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.STM32H750xB devices incorporate high-speed embedded memories with a Flash memory of 128 Kbytes, 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2×32-bit multi-AHB bus matrix and a multi-layer AXI interconnect supporting internal and external memory access.All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor control, five low-power timers, a true random number generator (RNG), and a cryptographic acceleration cell. The devices support four digital filters for external sigma-delta modulators (DFSDM). They also feature standard and advanced communication interfaces.Standard peripheralsFour I2CsFour USARTs, four UARTs and one LPUARTSix SPIs, three I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S peripherals can be clocked by a dedicated internal audio PLL or by an external clock to allow synchronizationFour SAI serial audio interfacesOne SPDIFRX interfaceOne SWPMI (Single Wire Protocol Master Interface)Management Data Input/Output (MDIO) slavesTwo SDMMC interfacesA USB OTG full-speed and a USB OTG high-speed interface with full-speed capability (with the ULPI)One FDCAN plus one TT-CAN interfaceAn Ethernet interfaceChrom-ART AcceleratorHDMI-CECAdvanced peripherals includingA flexible memory control (FMC) interfaceA Quad-SPI Flash memory interfaceA camera interface for CMOS sensorsAn LCD-TFT display controllerA JPEG hardware compressor/decompressorDedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages except LQFP100 to allow a greater power supply choice.A comprehensive set of power-saving modes allows the design of low-power applications.
Core
- 32bit Arm Cortex-M7 core with double precision FPU and L1 cache: 16Kbytes of data and 16Kbytes of instruction cache; frequency up to 400MHz, MPU, 856DMIPS/2.14DMIPS/MHz (Dhrystone 2.1), and DSP instructions
Memories
- Dual mode Quad-SPI memory interface running up to 133MHz
- Flexible external memory controller with up to 32bit data bus:
- SRAM, PSRAM, NOR Flash memory clocked up to 133MHz in synchronous mode
- SDRAM/LPSDR SDRAM
- 8/16bit NAND Flash memories
Security
- ROP, PC-ROP, active tamper, secure firmware upgrade support, Secure access mode
General-purpose input/outputs
- Up to 168 I/O ports with interrupt capability
Reset and power management
- 3 separate power domains which can be independently clock-gated or switched off
- 1.62 to 3.6V application supply and I/Os
- POR, PDR, PVD and BOR
- Dedicated USB power embedding a 3.3V internal regulator to supply the internal PHYs
- Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
- Voltage scaling in Run and Stop mode (5 configurable ranges)
- Backup regulator (~0.9V)
- Voltage reference for analog peripheral/VREF+
- Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging
Low-power consumption
- Total current consumption down to 4µA
Clock management
- Internal oscillators: 64MHz HSI, 48MHz HSI48, 4MHz CSI, 32kHz LSI
- External oscillators: 4-48MHz HSE, 32.768kHz LSE
- 3 PLLs with Fractional mode
Interconnect matrix
- 3 bus matrices (1 AXI and 2 AHB)
- Bridges (5x AHB2-APB, 2x AXI2-AHB)
4 DMA controllers to unload the CPU
- 1x high-speed master direct memory access controller (MDMA) with linked list support
- 2x— dual-port DMAs with FIFO
- 1x— basic DMA with request router capabilities
11 analog peripherals
- 3x ADCs with 16bit max. resolution (up to 36 channels, 4.5MSPS at 12bits)
- 1x temperature sensor
- 2x 12bit D/A converters(1MHz)
- 2x ultra-low-power comparators
- 2x operational amplifiers (8MHz bandwidth)
- 1x digital filters for sigma delta modulator(DFSDM) with 8 channels/4 filters
Graphics
- LCD-TFT controller up to XGA resolution
- Chrom-ART graphical hardware Accelerator (DMA2D) to reduce CPU load
- Hardware JPEG Codec
Up to 22 timers and watchdogs
- 1x high-resolution timer (2.5ns max resolution)
- 2x 32bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 200MHz)
- 2x 16bit advanced motor control timers (up to 200MHz)
- 10x 16bit general-purpose timers (up to 200MHz)
- 5x 16bit low-power timers (up to 200MHz)
- 2x watchdogs (independent and window)
- 1x SysTick timer
- RTC with sub-second accuracy & HW calendar
Cryptographic acceleration
- AES 128, 192, 256, TDES
- HASH (MD5, SHA-1, SHA-2), HMAC
- True random number generators
Debug mode
- SWD & JTAG interfaces
- 4-Kbyte Embedded Trace Buffer
96-bit unique ID
All packages are ECOPACK2 compliant
