Описание
Based on the ARM926EJ-S processor, the SAM9CN12 devices offer the frequently-requested combination of user interface functionality and high data rate connectivity, with LCD Controller, resistive touch-screen, multiple UARTs, SPI, I²C, full-speed USB Host and Device and SDIO. The SAM9CN12 support the latest generation of LPDDR/DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multilayer bus architecture associated with eight DMA channels and distributed memory – including a 32-Kbyte SRAM – sustains the high bandwidth required by the processor and the high-speed peripherals.
- Core
- ARM926EJ-S™ ARM® Thumb® Processor running up to 400 MHz
- 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
- Memories
- One 128-Kbyte internal ROM embedding standard or secure bootstrap routine.
- One 32-Kbyte internal SRAM, single-cycle access at system speed
- 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories
- MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC)
- System running up to 133 MHz
- Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real Time Clock
- Boot Mode Select Option, Remap Command
- Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
- Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL optimized for USB
- Six 32-bit-layer AHB Bus Matrix
- Dual Peripheral Bridge with dedicated programmable clock
- One dual port 8-channel DMA Controller
- Advanced Interrupt Controller and Debug Unit
- Two Programmable External Clock Signals
- Low-power Mode
- Shut Down Controller with four 32-bit battery backup registers
- Clock Generator and Power Management Controller
- Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
- Peripherals
- LCD Controller
- USB Device Full Speed with dedicated On-Chip Transceiver
- USB Host Full Speed with dedicated On-Chip Transceiver
- One High speed SD card and SDIO Host Controller
- Two Master/Slave Serial Peripheral Interfaces
- Two Three-channel 32-bit Timer/Counters
- One Synchronous Serial Controller
- One Four-channel 16-bit PWM Controller
- Two Two-wire Interfaces
- Four USARTs, two UARTs, one DBGU
- One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touch screen support
- Safety
- Crystal Failure Detection
- Independent Watchdog
- Power-on Reset Cells
- Write Protection Registers
- Cryptography
- TRNG True Random Number Generator compliant with NIST Special Publication 800-22
- AES 256-, 192-, 128-bit Key Algorithm compliant with FIPS Publication 197 (except for SAM9N12)
- 256 Fuse bits for crypto key and 64 Fuse bits for device configuration, including JTAG disable and forced boot from the on-chip ROM
- I/O
- Four 32-bit Parallel Input/Output Controllers
- 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
- Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input
- Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output
